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-- Contador ascendente 4 bit con 1 Hz de reloj,
-- con salida hexadecimal en display de 7 segmentos
--Nombre de modulo: counter_4b_7seg
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter_4b_7seg is
Port (clock_50Mhz : in STD_LOGIC; reset: in bit;
7SEG: OUT STD_LOGIC_VECTOR (7 downto 0);
END counter_4b_7seg;ARCHITECTURE rtl OF counter_4b_1hz IS
SIGNAL clkout: std_logic;
CONSTANT max: INTEGER := 50000000;
CONSTANT half: INTEGER := max/2;
SIGNAL count: INTEGER RANGE 0 TO max;
SIGNAL F: INTEGERRANGE 0 to 15
BEGIN
-- generando señal clock de 1Hz de frecuencia
PROCESS
BEGIN
WAIT UNTIL clock_50Mhz'EVENT and clock_50Mhz = '1';
IF count < max THEN count <= count + 1; ELSE count <= 0;
END IF;
IF count < half THEN clkout <= '0';
ELSE clkout <= '1';
END IF;
END PROCESS;
--contador 4 bits ascendente
PROCESS(clkout,reset)
VARIABLEcuenta: INTEGER RANGE 0 TO 15;
BEGIN
IF (reset='1') THEN
cuenta:=0;
ELSIF (clkout'EVENT AND clkout='0') THEN
cuenta:=cuenta+1; END IF;
F <= cuenta;
BEGIN
case F is
when 0 => 7SEG :="10000001";
when 1 => 7SEG :="11001111";
when 2 => 7SEG :="10010010";
when 3 => 7SEG:="10000110";
when 4 => 7SEG :="11001100";
when 5 => 7SEG :="10100100";
when 6 => 7SEG :="11100000";
when 7 => 7SEG :="10001111";
when 8 => 7SEG :="10000000"; when 9 => 7SEG :="10000100";
when 10 => 7SEG :="11100010";
when 11 => 7SEG :="11100000";
when 12 => 7SEG :="11110010";
when 13 => 7SEG :="11000010";...
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