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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

A 20-Gb/s Adaptive Equalizer in 0.13-m CMOS Technology
Jri Lee, Member, IEEE
Abstract—An adaptive equalizer incorporates spectrum-balancing technique to achieve high speed and low power dissipation. Obviating the need for slicers, this circuit compares the low and high frequency components of the data spectrum andadjusts the boosting accordingly. Fabricated in 0.13- m CMOS technology, this circuit achieves a data rate of 20 Gb/s while consuming 60 mW from a 1.5-V supply. Index Terms—Adaptive equalizer, capacitive degeneration, equalizing filter, power detector.

I. INTRODUCTION IGH-SPEED equalizers have found extensive usage in modern broadband data communications. Recent research has reported 10-Gb/sadaptive equalizers [1], [2] in 0.13- m CMOS and 150-GHz BiCMOS technologies. However, some advanced applications would require equalizers to operate at even higher speed. For example, systems such as military radars, airborne platforms, and telescope arrays would need to transmit digital data (i.e., the output of the receiver front end) across cables at a rate of tens of gigabits per second. Fig. 1illustrates a possible configuration of a microwave telescope array. The A/D converters quantize the signal from antennae and deliver the digitized outputs for signal processing. Due to the large physical dimensions of the antenna disks, the data would need to travel across at least several meters of coaxial cables such that all of them could be fed into one single processor for real-timecorrelation. As a result, a high-speed equalizer along with a clock and data recovery circuit becomes essential here. The severe environment (e.g., large variation of outdoor temperature and impure power supply) necessitates a high-performance equalizer design with adaptability and robustness. This paper presents a new approach to the operation of adaptive equalizers. A self-comparison method in thefeedback path obviates the need for slicers to achieve a higher speed with minimum power. Fabricated in 0.13- m CMOS technology, this circuit is capable of recovering 20-Gb/s data distorted from transmitting through a 5-meter long AWG18 cable, presenting a peak-to-peak jitter of 14 ps with a power dissipation of 60 mW. The next section presents the analysis of cable equalization and develops thefoundation for the proposed topology. Section III describes the design of building blocks in transistor level, and Section IV summarizes the experimental results.
Manuscript received September 8, 2005; revised April 4, 2006. The author is with the Electrical Engineering Department, National Taiwan University, Taipei, Taiwan 106, R.O.C. (e-mail: jrilee@cc.ee.ntu.edu.tw). Digital Object Identifier10.1109/JSSC.2006.880629

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Fig. 1. Possible realization of a microwave telescope array.

II. CHANNEL CHARACTERISTICS In order to quantify the magnitude attenuation and phase deviation of the channel, we must investigate the characteristic of it, and develop models so as to provide an emulated input signal for the equalizer design. The loss of coaxial cables and backplane traces is a function oflength and frequency. It is usually represented as (1) where and are coefficients denoting skin effect and dielectric loss, respectively, and the cable/trace length. At low frequencies, the substrate conductance contributes negligible loss compared with the skin effect, yielding a simplified transfer function of the channel (2) Here, the magnitude and phase are bound together: the 10-dB and 20-dB losscorrespond to phase shifts of 66 and 132 , respectively, regardless of the length and frequency. As frequency increases, the dielectric loss becomes significant, leading to a more rapid drop in magnitude. A typical transfer function is depicted in Fig. 2. In order to specify the critical point where the skin effect and dielectric losses are equivalent in magnitude, we . Note that this critdefine...