Manual verilog

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  • Publicado : 27 de agosto de 2012
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Tutorial 1: schematic design and Verilog test bench. This tutorial is meant to be a guide for typical basic schematic design. It shows the software tools required to simulate and test the behavior ofyour design. For this tutorial you must have Xilinx ISE Design Suite installed in your computer. You can download it from Now, first thing to do islaunch the ISE software, double-clicking the ISE project navigator on your program list .

Creating a new project: 1. Select File → New Project, and the New Project Wizard will appear. You shouldenter a name for your project and choose a location. Then select the type of top-level source for the project which in this case is a schematic source. 2. In the project settings window select theproperties according to your needs and then click next and finish. Next you should create a source file to develop the schematic: 1. Select Project → New source, and the New Source Wizard window willappear.

Figure 1. New source wizard window. 2. Choose the source type, which in this case it should be a Schematic file. 3. Write a file name and a location for it, and select the “Add to project” box.In this tutorial we are going to develop a schematic for a comparator of three bits numbers so we will call the file “comparator”. The comparator output will be 1 if the numbers are the same and 0otherwise. 4. Click next and finish.

The Xilinx schematic capture tool opens and then is time to insert components and interconnect them to develop the design. To do so, select the symbols tab locatedin the bottom left part of the window. When the symbol window appears you can select the inputs and outputs of your design and the logic gates needed. In this case we are going to use XNOR and ANDcomponents. Use the add wire icon marker Figure 2. Symbols window. The symbols are placed in the comparator.sch file and figure 3 shows the final design. to connect the components and the I/O

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