Comparador Datasheet

DM74LS85 4-Bit Magnitude Comparator

August 1986 Revised March 2000

DM74LS85 4-Bit Magnitude Comparator
General Description
These 4-bit magnitude comparators perform comparison of straightbinary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits withoutexternal gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to thecorresponding inputs of the next stage handling more-significant bits. The stage handling the leastsignificant bits must have a high-level voltage applied to the A = B input. The cascading path is implementedwith only a two-gate-level delay to reduce overall comparison times for long words.

Features
s Typical power dissipation 52 mW s Typical delay (4-bit words) 24 ns

Ordering Code:
Order NumberDM74LS85M DM74LS85N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001,0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation

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DM74LS85

Function Table
Comparing Inputs A3, B3 A3 > B3 A3 < B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A2, B2X X A2 > B2 A2 < B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0,B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A>B X X X X X X X X H L L X H L Cascading Inputs AB H L H L H L H L H L L L L H AB A=B tPHL Propagation Delay Time...