CMOS Decade Counter/Divider
CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. This device is particularly advantageous in display applications where low power dissipation and/or low package count is important. A high RESETsignal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter,thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment outputs go high onselection.
• High Voltage Types (20V Rating) • Decoded 7 Segment Display Outputs and Ripple Blanking • Counter and 7 Segment Decoding in One Package • Easily Interfaced with 7 Segment Display Types • Fully Static Counter Operation DC to 6MHz (typ.) at VDD = 10V • Ideal for Low-Power Displays • “Ripple Blanking” and Lamp Test • 100% Tested for Quiescent Current at 20V • StandardizedSymmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Schmitt-Triggered Clock Inputs • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Speciﬁcations for Description of “B” Series CMOS Device’s
• Decade Counting 7 Segment Decimal Display • Frequency Division 7 Segment Decimal Displays • Clocks, Watches, Timers (e.g. ÷ 60, ÷ 60, ÷12 Counter/Display • Counter/Display Driver For Meter Applications
CD4033BMS TOP VIEW
VDD 16 1 CLOCK 1 CLOCK INHIBIT 2 16 VDD 15 RESET 14 LAMP TEST 13 c 12 b 11 e 10 a 9 d 3 RIPPLE BLK IN 8 VSS LAMP TEST RESET 14 CLOCK INHIBIT 15 CLOCK 2 10 a 12 b 13 c 9 d 11 e 6 f 7 DECODED OUTPUTS
RIPPLE BLANKING IN 3 RIPPLE BLANKING OUT 4 CARRY OUT 5 f 6 g 7 VSS 8
7 g 5 CARRY OUT 4RIPPLE BLK OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
The CD4033BMS has provisions for automatic blanking of the non-signiﬁcant zeros in a multi-digit decimal number which results in an easily readable displayconsistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be displayed as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the CD4033BMS associated with the most signiﬁcant digit in the display to a low-level voltage and connecting the RBO terminal of that stage to the RBI terminal of the CD4033BMS in thenext-lower signiﬁcant position in the display. This procedure is continued for each succeeding CD4033BMS on the interger side of the display. On the fraction side of the display the RBI of the CD4033BMS associated with the least signiﬁcant bit is connected to a low-level voltage and the RBO of that CD4033BMS is connected to the RBI terminal of the CD4033BMS in the next more-signiﬁcant-bit position. Again,this procedure is continued for all CD4033BMS’s on the fraction side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more-signiﬁcant-stage). For example: optional zero → 0.7346. Likewise, the zero in a number such as 763.0 can be displayed...