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INTEGRATED CIRCUITS

DATA SHEET

TDA8051 QPSK receiver
Product specification Supersedes data of 1998 Jan 08 File under Integrated Circuits, IC02 1999 Aug 20

Philips Semiconductors

Product specification

QPSK receiver
FEATURES • High operating input sensitivity • Gain controlled amplifier • PLL controlled carrier frequency • Low crosstalk between I and Q channel outputs • 3-wiretransmission bus • 5 V supply voltage. APPLICATIONS • BPSK/QPSK demodulation. GENERAL DESCRIPTION

TDA8051

This TDA8051 is a monolithic bipolar IC intended for Quadrature Phase Shift Key (QPSK) demodulation. It includes: • Low noise RF and gain controlled amplifier • Two matched mixers • Symmetrical Voltage Controlled Oscillator (VCO) with 0 to 90° signal generator whose frequency is controlled byan integrated Phase Lock Loop (PLL) circuit. • Two matched amplifiers for output base-band active filtering and output buffers The gain control is produced by output level detection compared with an external pre-fixed reference. The PLL consists of: • Divide by four preamplifier • 12-bit programmable main divider • Crystal oscillator with 8-bit programmable reference divider • Phase/frequencydetector combined with charge pump to drive tuning amplifier • 30 V output

QUICK REFERENCE DATA All AC units are RMS values unless otherwise specified. SYMBOL VCC fI(LNA) VI(LNA) ∆ΦI-Q ∆GI-Q αCT(I-Q) IM3 Vo fstep fxtal Tamb PARAMETER supply voltage range input carrier frequency at LNA input input level at LNA input phase error between I and Q channels gain error between I and Q channels crosstalkbetween I and Q channels 3rd-order intermodulation distortion in I and Q channels (0 dBmV at LNA_IN) voltage output on pin I_OUT and Q_OUT step at output crystal frequency operating ambient temperature MIN. 4.75 44 −30 − − − − − 50 1 0 − − ±3 ±1 −30 − 48 − − − TYP. 5.00 MAX. 5.25 130 0 − − − −45 − 250 4 70 V MHz dBmV deg dB dBc dBc dBmV kHz MHz °C UNIT

ORDERING INFORMATION PACKAGE TYPE NUMBERNAME TDA8751T SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT287-1

1999 Aug 20

2

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Q_OUT1 I_IN1 A1VCC 6 9 LNA_IN 8 LNA_OUT DEMOD_IN CLK DATA EN TUNE CP DIGITAL PHASE COMPARATOR PROGRAMMABLE MAIN DIVIDER 1/4 7 14 15 16 19 18 21 22 TKB TKA 3-WIRE BUS TRANSCEIVER 90¡ 1/2 A2VCC 23 A3VCC 25 DVCC 13OUTVCC 27 AGC_IN 11 I_OUT1 5 Q_IN1 28 29 4 3 1 2 I_OUT2 I_OUT I_OUTC Q_OUT Q_OUTC Q_OUT2

BLOCK DIAGRAM

Philips Semiconductors

QPSK receiver

× ×
TDA8051


32 31 30

Fig.1 Block diagram.

handbook, full pagewidth

3

CHARGE

PROGRAMMABLE REF DIVIDER

1/2

12

OSC_IN

17 TEST n.c.

10 A1GND

24

26

20
FCE112

A2GND OUTGND

DGND

Productspecification

TDA8051

Philips Semiconductors

Product specification

QPSK receiver
PINNING SYMBOL I_OUT I_OUTC I_OUT2 I_IN1 I_OUT1 A1VCC DEMOD_IN LNA_OUT LNA_IN A1GND AGC_IN OSC_IN DVCC CLK DATA EN TEST CP TUNE DGND TKB TKA A2VCC A2GND A3VCC OUTGND OUTVCC Q_OUT1 Q_IN1 Q_OUT2 Q_OUTC Q_OUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION I databuffered balanced output I data buffered balanced output I data filtered output input to active filter amplifier for I data I data raw output analog supply voltage 1 demodulator RF input low noise amplifier RF output low noise amplifier RF input analog ground 1 AGC control voltage input oscillator input digital supply voltage 3-wire bus serial control clock 3-wire bus serial control data 3-wire bus...
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