Mecanica

DM74LS90 Decade and Binary Counters

August 1986 Revised March 2000

DM74LS90 Decade and Binary Counters
General Description
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zeroreset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the DM74LS90 countersby connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Features
s Typical power dissipation 45 mW s Count frequency 42 MHz

Ordering Code:
Order Number DM74LS90M DM74LS90N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead PlasticDual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Reset/Count Truth Table
Reset Inputs R0(1) H H X X L L X R0(2) H H X L X X L R9(1) L X H X L X L R9(2) X L H L X L X QD L L H Output QC L L L QB L L L QA L L H

COUNT COUNT COUNT COUNT

© 2000 FairchildSemiconductor Corporation

DS006381

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Function Tables
BCD Count Sequence (Note 1) Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H QC L L L L H H H H L L Output QB L L H H L L H H L L QA L H L H L H L H L H

Logic Diagram

Bi-Quinary (5-2) (Note 2) Count QA 0 1 2 3 4 5 6 7 8 9
H = HIGH Level L = LOW Level X = Don’t Care Note 1: Output QA is connected toinput B for BCD count. Note 2: Output QD is connected to input A for bi-quinary count. Note 3: Output QA is connected to input B. The J and K inputs shown without connection are for reference only and are functionally at a high level.

Output QD L L L L H L L L L H QC L L H H L L L H H L QB L H L H L L H L H L L L L L L H H H H H

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Absolute MaximumRatings(Note 4)
Supply Voltage Input Voltage (Reset) Input Voltage (A or B) Operating Free Air Temperature Range Storage Temperature Range 7V 7V 5.5V 0°C to +70°C −65°C to +150°C
Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “ElectricalCharacteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 5) ClockFrequency (Note 6) Pulse Width (Note 5) A to QA B to QB A to QA B to QB A B Reset tW Pulse Width (Note 6) A B Reset tREL tREL TA Reset Release Time (Note 5) Reset Release Time (Note 6) Free Air Operating Temperature 0 0 0 0 15 30 15 25 50 25 25 35 0 70 ns ns °C ns ns Parameter Min 4.75 2 0.8 −0.4 8 32 16 20 10 MHz Nom 5 Max 5.25 Units V V V mA mA MHz

Note 5: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC =5V. Note 6: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current...