Teoria De Restricciones

G-5

Drum-Buffer-Rope Implementation for Semiconductor Manufacturing
Sue Ellen Swink, Absalon Lyra, and Neal G. Pierce

ABSTRACT
The Drum-Buffer-Rope methodology from the Theory of Constraints is adapted to a research manufacturing environment with re-entrant flows. The authors begin with an overview of semiconductor manufacturing practices and the production control/lot start algorithmscurrently in use within this industry. A brief introduction to semiconductor wafer manufacturing and Motorola’s Advanced Products Research and Development Laboratory’s (APRDL) environment is also included. The Drum-Buffer-Rope methodology is described first for a manufacturing line which does not have re-entrant flows. The Drum-BufferRope methodology is then adapted to account for re-entrant flowsby calculating the workload on the bottleneck equipment in the facility and allocating WIP accordingly. This approach allows APRDL to quickly accept or reject jobs based on their effect on the bottleneck/constraint and has helped increase throughput by 150% and reduce cycle time by 20% at Motorola’s Advanced Products Research and Development Laboratory in Austin, Texas. This dynamic productioncontrol system enables better production scenarios. Ancillary benefits to internal and external customers, now and in the future, are explored.

KEYWORDS
Drum-Buffer-Rope, Production Control, Re-Entrant Flow Manufacturing, Theory of Constraints, and Semiconductor Wafer Manufacturing.

by all lots requiring a certain workstation. Process flows generate repetitive lot movements through a sequenceof equipment groups in which a lot may visit the same workstation as many as 25 times during the process cycle. Lots with different maturity will queue and compete for similar workstations due to the highly re-entrant flow, characteristic of semiconductor manufacturing. Most semiconductor facilities use a job-shop or farm (chickens with the chickens while the pigs are with the pigs) layout for easeof equipment installation, maintenance, and flexibility to accommodate process flow changes. This layout configuration and the existence of a highly re-entrant flow cause lots to travel long distances within a relatively small cleanroom area (30,000 to 80,000 square feet) during the process cycle. Semiconductor factories can theoretically produce a finished wafer within a few days under idealconditions, although today’s more sophisticated devices may require >15 days of pure processing time. However, manufacturers (usually in operation seven days per week, 24 hours a day) may measure actual cycle times in weeks or even months. These long queue times are attributable to system variability such as product mix, process instability, unscheduled down time, or product quality problems.Mismatched equipment run rates, variable load sizes, varied product dispatch strategies at each workstation, and long process times of batch operations create an asynchronous system increasing queue times that greatly contribute to increases of cycle time (Pierce and Stafford).

APRDL Environment INTRODUCTION
The production of semiconductors is a challenging technological process. The success ofoperations management and production control techniques are critically dependent upon the availability and performance of highly sophisticated, very expensive process equipment. However, effective order release, handling, and dispatching of material are also crucial in performing as a world-class manufacturer. The Advanced Products Research and Development Laboratory’s (APRDL) pilot line wafer fab mustdeal with these manufacturing challenges with the additional demands of developing and transferring leading-edge, cost-effective technologies. Numerous experiments in the form of lot splits are conducted. These “child” lots require more resources and can generate substantial cycle time due to non-standard processing. In comparison with a manufacturing facility, APRDL processes a larger amount...