Vhdl
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Publicado: 21 de mayo de 2012
A
Examples A
This appendix presents examples that demonstrate basic concepts of Synopsys FPGA Compiler II / FPGA Express: • • • • • • • • • Moore Machine Mealy MachineRead-Only Memory Waveform Generator Smart Waveform Generator Definable-Width Adder-Subtracter Count Zeros—Combinational Version Count Zeros—Sequential Version Soft Drink Machine—StateMachine Version
Examples A-1
• • • • •
Soft Drink Machine—Count Nickels Version Carry-Lookahead Adder Serial-to-Parallel Converter—Counting Bits Serial-to-ParallelConverter—Shifting Bits Programmable Logic Arrays
Moore Machine
Figure A-1 is a diagram of a simple Moore finite state machine. It has one input (X), four internal states (S0to S3), and one output (Z).
Figure A-1 Moore Machine Specification
0 S0 0 0 1 Present state S0 S1 S2 S1 1 1 S2 1 S3 Next Output state (Z) X=0 X=1 X=0 S0 S0 S2 S3 S2 S2 S3 S10 1 1 0
0 1 S3 0 1
0
The VHDL code implementing this finite state machine is shown in Example A-1, which includes a schematic of the synthesized circuit.
Examples A-2 The machine description includes two processes. One process defines the synchronous elements of the design (state registers); the other process defines the combinationalpart of the design (state assignment case statement). For more details on using the two processes, see “Combinational Versus Sequential Processes” on page 5-55.
Example A-1Implementation of a Moore Machine
entity MOORE is port(X, CLOCK: in BIT; Z: out BIT); end MOORE; -- Moore machine
architecture BEHAVIOR of MOORE is type STATE_TYPE is (S0, S1,S2, S3); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin -- Process to hold combinational logic COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => Z
Examples A
This appendix presents examples that demonstrate basic concepts of Synopsys FPGA Compiler II / FPGA Express: • • • • • • • • • Moore Machine Mealy MachineRead-Only Memory Waveform Generator Smart Waveform Generator Definable-Width Adder-Subtracter Count Zeros—Combinational Version Count Zeros—Sequential Version Soft Drink Machine—StateMachine Version
Examples A-1
• • • • •
Soft Drink Machine—Count Nickels Version Carry-Lookahead Adder Serial-to-Parallel Converter—Counting Bits Serial-to-ParallelConverter—Shifting Bits Programmable Logic Arrays
Moore Machine
Figure A-1 is a diagram of a simple Moore finite state machine. It has one input (X), four internal states (S0to S3), and one output (Z).
Figure A-1 Moore Machine Specification
0 S0 0 0 1 Present state S0 S1 S2 S1 1 1 S2 1 S3 Next Output state (Z) X=0 X=1 X=0 S0 S0 S2 S3 S2 S2 S3 S10 1 1 0
0 1 S3 0 1
0
The VHDL code implementing this finite state machine is shown in Example A-1, which includes a schematic of the synthesized circuit.
Examples A-2 The machine description includes two processes. One process defines the synchronous elements of the design (state registers); the other process defines the combinationalpart of the design (state assignment case statement). For more details on using the two processes, see “Combinational Versus Sequential Processes” on page 5-55.
Example A-1Implementation of a Moore Machine
entity MOORE is port(X, CLOCK: in BIT; Z: out BIT); end MOORE; -- Moore machine
architecture BEHAVIOR of MOORE is type STATE_TYPE is (S0, S1,S2, S3); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin -- Process to hold combinational logic COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => Z
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