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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4060 14-stage binary ripple counter with oscillator
Product specification File under Integrated Circuits, IC06 December 1990

PhilipsSemiconductors

Product specification

14-stage binary ripple counter with oscillator
FEATURES • All active components on chip • RC or crystal oscillator configuration • Output capability: standard (except for RTC and CTC) • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4060 are high-speed Si-gate CMOS devices and are pin compatible with “4060” of the “4000B” series. They are specified incompliance with JEDEC standard no. 7A. The 74HC/HCT4060 are 14-stage ripple-carry counter/dividers and oscillators with three oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

74HC/HCT4060

terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RCor crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case keep the other oscillator pins (RTC and CTC) floating. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions. In the HCT version, the MR input is TTL compatible, butthe RS input has CMOS input switching levels and can be driven by a TTL output by using a pull-up resistor to VCC.

TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay RS to Q3 Qn to Qn+1 tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL ×VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 3. For formula on dynamic power dissipation see next pages. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. MR to Qn maximum clock frequency input capacitance power dissipation capacitance perpackage notes 1, 2 and 3 CONDITIONS HC CL = 15 pF; VCC = 5 V 31 6 17 87 3.5 40 31 6 18 88 3.5 40 ns ns ns MHz pF pF HCT UNIT

December 1990

2

Philips Semiconductors

Product specification

14-stage binary ripple counter with oscillator
PIN DESCRIPTION PIN NO. 1, 2, 3 7, 5, 4, 6, 14, 13, 15 8 9 10 11 12 16 SYMBOL Q11 to Q13 Q3 to Q9 GND CTC RTC RS MR VCC NAME AND FUNCTION counter outputscounter outputs ground (0 V) external capacitor connection external resistor connection clock input/oscillator pin master reset positive supply voltage

74HC/HCT4060

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

3

Philips Semiconductors

Product specification

14-stage binary ripple counter with oscillator
DYNAMIC POWER DISSIPATION FOR74HC PARAMETER total dynamic power dissipation when using the on-chip oscillator (PD) Note 1. GND = 0 V; Tamb = 25 °C DYNAMIC POWER DISSIPATION FOR 74HCT PARAMETER total dynamic power dissipation when using the on-chip oscillator (PD) Notes 1. GND = 0 V; Tamb = 25 °C 2. Where: fo = output frequency in MHz fosc = oscillator frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output loadcapacitance in pF Ct = timing capacitance in pF VCC = supply voltage in V VCC (V) 4.5 TYPICAL FORMULA FOR PD (µW) (note 1) VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1) 2.0 4.5 6.0

74HC/HCT4060

CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 60 × VCC CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc +...
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