Descripción del funcionamiento del dac

LTC2604/LTC2614/LTC2624 Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP FEATURES
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DESCRIPTION
The LTC®2604/LTC2614/LTC2624 are quad 16-,14- and 12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in 16-lead narrow SSOP packages. These parts have separate reference inputs for each DAC. They have built-in high performance output buffers and are guaranteed monotonic. These parts establishadvanced performance standards for output drive, crosstalk and load regulation in singlesupply, voltage output multiples. The parts use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisy-chain capability and a hardware CLR function are included. The LTC2604/LTC2614/LTC2624 incorporate a power-on reset circuit. During power-up, the voltageoutputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2604-1/LTC2614-1 /LTC2624-1 to midscale. The voltage outputs stay at midscale until a valid write and update take place.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks arethe property of their respective owners.

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Smallest Pin Compatible Quad 16-Bit DAC: LTC2604: 16-Bits LTC2614: 14-Bits LTC2624: 12-Bits Guaranteed 16-Bit Monotonic Over Temperature Separate Reference Inputs for each DAC Wide 2.5V to 5.5V Supply Range Low Power Operation: 250μA per DAC at 3V Individual DAC Power-Down to 1μA, Max Ultralow Crosstalk Between DACs ( 1GΩ) when thecorresponding DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-updelay time is 5μs. If on the other hand, all four DACs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power up delay time is 12μs (for VCC = 5V) or 30μs (for VCC = 3V). Voltage Outputs Each of the four rail-to-rail amplifiers contained in these parts has guaranteedload regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA.

2604fd

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CS/LD 2 7 13 14 17 D7
2604 F02a

OPERATION

SCK 3 4 10 21 D3 D2D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 16 20 22 C0 ADDRESS WORD A3 A2 A1 A0 D15 5 6 8 9 15 19 C1

1

SDI

C3

C2

COMMAND WORD

24-BIT INPUT WORD

Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word) LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don’t Care Bits LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits

CS/LD 6 7 13 14 17 D15 D14D13 D12 D11 D10 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 A3 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 22 20 15 19 X 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0

SCK

1

2

3

4

5

SDI

X

X

X

X

X

DON’T CARE

SDO

X

X

X

X

X

PREVIOUS 32-BIT INPUT WORDt1 t2 SCK SDI SDO 17 t3 D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18

CURRENT 32-BIT INPUT WORD
2604 F02b

Figure 2b. LTC2604 32-Bit Load Sequence LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t Care Bits LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits

LTC2604/LTC2614/LTC2624

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2604fd

LTC2604/LTC2614/LTC2624 OPERATION
DC output impedance is equivalent...