• Fast Read Access Time – 120 ns • Fast Byte Write – 200 µs or 1 ms • Self-timed Byte Write Cycle
– Internal Address and Data Latches – Internal Control Timer – Automatic Clear Before Write Direct Microprocessor Control – READY/BUSY Open Drain Output – DATA Polling Low Power – 30 mA Active Current – 100 µA CMOS Standby Current High Reliability – Endurance: 104 or 105 Cycles – DataRetention: 10 Years 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Commercial and Industrial Temperature Ranges
• • • • • • •
64K (8K x 8) Parallel EEPROMs AT28C64 AT28C64X
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-usefeatures. The device is manufactured with Atmel’s reliable nonvolatile technology. (continued)
Pin Name A0 - A12 CE OE WE I/O0 - I/O7 RDY/BUSY NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don’t Connect TSOP Top View
OE A11 A9 A8 NC WE VCC RDY/BUSY (or NC) A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 2726 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PDIP, SOIC Top View
RDY/BUSY (or NC) A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
LCC, PLCC Top View
A7 A12 RDY/BUSY (or NC) DC VCC WE NC I/O1 I/O2 VSS DC I/O3I/O4 I/O5 14 15 16 17 18 19 20
A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A8 A9 A11 NC OE A10 CE I/O7 I/O6
Note: PLCC package pins 1 and 17 are DON’T CONNECT.
The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address anddata are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Pollingof I/O7 . Once the end of a write
cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 µA. Atmel’s AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally forextended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
READ: The AT28C64 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at...